View LTC3118-15_8910594.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 for more information www.linear.com/ltc3118 typical a pplica t ion fea t ures descrip t ion 18v, 2a buck-boost dc/dc converter with low-loss dual input powerpath the lt c ? 3118 is a dual-input, wide voltage range syn- chronous buck -boost dc/dc converter with an intelligent, integrated, low-loss powerpath control. the unique power switch architecture provides efficient operation from either input source to a programmable output voltage above, below or equal to the input. voltage capability of up to 18v provides flexibility and voltage margin for a wide variety of applications and power sources. the ltc3118 uses a low noise, current mode architecture with a fixed 1.2 mhz pwm mode frequency that minimizes the solution footprint. for high efficiency at light loads, automatic burst mode operation can be selected consum - ing only 50a of quiescent current in sleep. system level features include ideal diode or v in priority modes, v in and v out power good indicators, accurate run comparators to program independent uvlo thresholds, and output disconnect in shutdown. other features include 2a shutdown current, short-circuit protection, soft-start, current limit and thermal overload protection. the ltc3118 is offered in thermally enhanced 24-lead 4mm 5mm qfn and 28-lead tssop packages. a pplica t ions n integrated high effciency dual input powerpath? plus buck-boost dc/dc converter n ideal diode or priority v in select modes n v in1 and v in2 range: 2.2v to 18v n v out range: 2v to 18v n either v in can be above, below or equal to v out n generates 5v at 2a for v in > 6v n 1.2mhz low noise fixed frequency operation n current mode control n all internal n-channel mosfets n pin-selectable pwm or burst mode ? operation n accurate, independent run pin thresholds n up to 94% effciency n v in and v out power good indicators n i q of 50a in sleep, 2a in shutdown n 4mm 5mm 24-lead qfn or 28-lead tssop packages n systems with multiple input sources n back up power systems n wall adapter or li-ion(s) input to 5v out n battery or super capacitor input for reserve power n replace diode-or designs with higher effciency, flexibility and performance l , lt , lt c , lt m , linear technology, the linear logo and burst mode are registered trademarks and powerpath and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s . patents, including 7709976. control signals 3.3h 0.1f 0.1f 400k 40.2k 47nf 22f 22f 100f indicators 4.7f 10nf 22pf bst1 bst2 v in1 v in2 v in1 v in2 sw1 sw2 3118 ta01a cm1 47nf cm2 cp1 v out v out 5v vc v1gd fb v2gd pgd mode sel run1 run2 cn1 10nf cn2 cp2 pgnd v cc gnd ltc3118 1.8nf 100k 100s/div 3118 ta01b 5v out ac-coupled 500mv/div sw1 10v/div sel 5v/div select v in2 select v in1 v in1 = 5v, v in2 = 12v, v out = 5v at 1a input switchover response ltc 3118 3118f
2 for more information www.linear.com/ltc3118 a bsolu t e maxi m u m r a t ings p in c on f igura t ion v in 1 , v in 2 voltage ....................................... C 0.3 v to 20 v v out voltage .............................................. C 0.3 v to 20 v sw1 dc voltage ( note 4) ............... C 0.3 v to ( v in 1 + 0.3 v) or ( v in 2 + 0.3 v) sw2 dc voltage ( note 4) ............. C0.3 v to (v out + 0.3 v) bst 1 voltage ..................... ( sw1 C 0.3v) to (sw1 + 6v) bst 2 voltage .................... ( sw2 C 0.3v) to (sw2 + 6v) run 1, run 2 voltage .................................. C 0.3 v to 20 v pgd , v1 gd , v2 gd voltage ......................... C 0.3 v to 20 v cm 1, cm 2 voltage ....................................... C 0.3 to 20 v (note 1) o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3118eufd#pbf ltc3118eufd#trpbf 3118 24-lead (4mm 5mm) plastic qfn C40c to 125c ltc3118iufd#pbf ltc3118iufd#trpbf 3118 24-lead (4mm 5mm) plastic qfn C40c to 125c ltc3118hufd#pbf ltc3118hufd#trpbf 3118 24-lead (4mm 5mm) plastic qfn C40c to 150c ltc3118mpufd#pbf ltc3118mpufd#trpbf 3118 24-lead (4mm 5mm) plastic qfn C55c to 150c ltc3118efe#pbf ltc3118efe#trpbf 3118fe 28-lead plastic tssop C40c to 125c ltc3118ife#pbf ltc3118ife#trpbf 3118fe 28-lead plastic tssop C40c to 125c ltc3118hfe#pbf ltc3118hfe#trpbf 3118fe 28-lead plastic tssop C40c to 150c ltc3118mpfe#pbf ltc3118mpfe#trpbf 3118fe 28-lead plastic tssop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 8 9 top view 25 pgnd ufd package 24-lead (4mm 5mm) plastic qfn 10 11 12 24 23 22 21 20 6 5 4 3 2 1 sel v in1 run1 run2 v cc mode gnd cp2 v in2 sw1 bst1 bst2 sw2 v out cp1 cn1 cm1 cm2 cn2 vc fb v1gd v2gd pgd 7 14 15 16 17 18 19 13 t jmax = 150c, jc = 3.4c/w, ja = 43c/w exposed pad ( pin 25) is pgnd, must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cm1 cn1 cp1 sel v in1 run1 run2 v cc mode gnd gnd vc fb v1gd cm2 cn2 pgnd cp2 v in2 sw1 bst1 bst2 sw2 v out pgnd pgnd pgd v2gd 29 pgnd t jmax = 150c, jc = 5c/w, ja = 30c/w exposed pad ( pin 29) is pgnd, must be soldered to pcb cp 1 voltage ........................ ( v in 1 C 0.3 v) to (v in 1 + 6v) cp 2 voltage ........................ ( v in 2 C 0.3 v) to (v in 2 + 6v) v cc , cn 1, cn2 voltage ................................... C 0.3 to 6v mode , sel , fb , vc voltage ........................... C 0.3 to 6v operating junction temperature range ( notes 2, 3) ltc 3118 e / ltc 3118 i ........................... C4 0 c to 125 c ltc 3 118 h .......................................... C 40 c to 150 c ltc 3 118 mp ........................................ C5 5 c to 150 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) tssop ...... 30 0 c ltc 3118 3118f
3 for more information www.linear.com/ltc3118 e lec t rical c harac t eris t ics parameter conditions min typ max units input operating voltage range v in1 or v in2 , v cc 2.5v l 2.2 18 v output operating voltage l 2 18 v undervoltage lockout threshold on v cc v cc rising, v in = 2.5v l 2.2 2.35 2.5 v minimum v in start-up voltage v cc powered from v in1 or v in2 (i vcc = 10ma) l 2.2 2.5 2.65 v input quiescent current in shutdown run1 and run2 < 0.2v 2 a input quiescent current in burst mode operation active v in1 or v in2 , fb = 1.2v 50 a inactive v in1 or v in2 , fb = 1.2v 5 a input quiescent current in pwm mode operation active v in1 or v in2 , fb = 0.8v 12 ma output quiescent current in burst mode operation 1 a oscillator frequency l 1000 1200 1400 khz oscillator frequency variation active v in = 3v to 18v 0.1 %/ v feedback voltage l 0.98 1.0 1.02 v feedback voltage line regulation active v in = 3v to 18v 0.2 % error amplifier transconductance vc current = 4a 80 s feedback pin input current fb = 1v 0 50 na vc source current vc = 0.5v, fb = 0.8v C14 a vc sink current vc = 0.5v, fb = 1.2v 14 a run pin threshold: accurate run1 or run2 rising l 1.17 1.22 1.27 v run pin hysteresis: accurate accurate run (rising C falling) 170 mv run pin logic threshold for v cc enable/shutdown l 0.2 0.65 1.15 v run pin leakage current run1 or run2 = 4v 0.2 a v cc output voltage i vcc = 1ma l 3.5 3.8 4.1 v v cc load regulation i vcc = 1ma to 10ma C1 % v cc line regulation i vcc = 1ma, v in = 5v to 18v 0.5 % v cc current limit v in > 6v 60 ma average inductor current limit (note 5) l 3.0 3.6 5.2 a overload current limit (note 5) current from v in1 or v in2 6 a reverse inductor current limit (note 5) pwm mode C200 ma maximum duty cycle percentage of period sw2 is low in boost mode l 90 95 % percentage of period sw1 is high in boost mode l 83 88 % minimum duty cycle percentage of period sw1 is high in buck mode l 0 % sw1 and sw2 forced low time bst1 or bst2 capacitor charge time 100 ns n-channel switch resistance switch a1 (from v in1 to sw1) 80 m switch a2 (from v in2 to sw1) 120 m switch b (from sw1 to pgnd) 80 m switch c (from sw2 to pgnd) 80 m switch d (from pv out to sw2) 80 m n-channel switch leakage v in2 , v in2 or v out = 18v 0.1 10 a soft-start time 1 ms mode and sel threshold voltage l 0.3 0.75 1.2 v mode and sel leakage pin = 5v 0 0.5 a the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t j t a = 25c (note 2). unless otherwise noted, v in1 or v in2 = 5v, v out = 5v. ltc 3118 3118f
4 for more information www.linear.com/ltc3118 typical p er f or m ance c harac t eris t ics v out = 12v, efficiency and power loss vs load current from v in1 v out = 12v, efficiency and power loss vs load current from v in2 12v out efficiency vs v in1 or v in2 voltage with 500ma and 1a load current parameter conditions min typ max units v in1 becomes active input in ideal diode mode v in2 = sel = 5v rising falling 5 4.2 5.4 4.6 5.8 5 v v pgd threshold per cent of fb voltage rising 90 94 98 % pgd hysteresis percent of fb voltage falling C2 % v1gd, v2gd, pgd low voltage i sink = 5ma 300 mv v1gd, v2gd, pgd leakage pin = 18v 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3118 is tested under pulsed load conditions such that t j t a . the ltc3112e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3118i is guaranteed to meet specifications over the C40c to 125c operating junction temperature, the ltc3118h is guaranteed to meet specifications over the C40c to 150c operating junction temperature range and the ltc3118mp is guaranteed and tested to meet specifications over the full C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for temperatures greater than 125c. the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t j t a = 25c (note 2). unless otherwise noted, v in1 or v in2 = 5v, v out = 5v. resistance and other environmental factors. the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (pd in watts) according to the following formula: t j = t a + (pd ? ja ) where ja is the thermal impedance of the package. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 4: voltage transients on the switch pins beyond the dc limit specified in the absolute maximum ratings, are non disruptive to normal operation when using good layout practices, as shown on the demo board or described in the data sheet and application notes. note 5: current measurements are performed when the ltc3118 is not switching. the current limit values measured in operation will be somewhat higher, while the reverse current thresholds may be lower due to the propagation delay of the comparators and inductor value. t a = 25c, unless otherwise noted. load current (a) 0.0001 efficiency (%) 40 60 10 3118 g01 20 0 0.001 0.01 0.1 1 100 30 50 10 70 80 90 5v in 12v in 18v in pwm burst loss pwm power loss (w) 2 3 1 0 5 4 load current (a) 0.0001 efficiency (%) pwm power loss (w) 40 60 10 3118 g02 20 0 0.001 0.01 0.1 1 100 30 50 10 70 80 2 3 1 0 5 4 90 5v in 12v in 18v in pwm loss burst input voltage (v) 2 efficiency (%) 90 18 3118 g03 80 70 4 12 14 16 6 8 10 100 85 95 75 v in1 , load = 500ma v in2 , load = 500ma v in1 , load = 1a v in2 , load = 1a ltc 3118 3118f
5 for more information www.linear.com/ltc3118 typical p er f or m ance c harac t eris t ics v out = 3.3v efficiency and power loss vs load current from v in1 v out = 3.3v efficiency and power loss vs load current from v in2 3.3v out efficiency vs v in1 or v in2 voltage with 500ma and 1a load current die temperature rise vs load current, v out = 12v, 4-layer ltc3118 demo board v out = 5v, efficiency and power loss vs load current from v in1 v out = 5v, efficiency and power loss vs load current from v in2 5v out efficiency vs v in1 or v in2 voltage with 500ma and 1a load current t a = 25c, unless otherwise noted. load current (a) 0.0001 efficiency (%) 40 60 10 3118 g04 20 0 0.001 0.01 0.1 1 100 30 50 10 70 80 90 pwm burst loss pwm power loss (w) 2 3 1 0 5 4 3.6v in 5v in 12v in load current (a) 0.0001 efficiency (%) 40 60 10 3118 g05 20 0 0.001 0.01 0.1 1 100 30 50 10 70 80 90 3.6v in 5v in 12v in pwm burst loss pwm power loss (w) 2 3 1 0 5 4 input voltage (v) 2 efficiency (%) 90 18 3118 g06 80 70 4 12 14 16 6 8 10 100 85 95 75 v in1 , load = 500ma v in2 , load = 500ma v in1 , load = 1a v in2 , load = 1a die temperature rise vs load current, v out = 5v, 4-layer ltc3118 demo board die temperature rise vs load current, v out = 3.3v, 4-layer ltc3118 demo board load current (a) 0.0001 efficiency (%) 40 60 10 3118 g07 20 0 0.001 0.01 0.1 1 100 30 50 10 70 80 90 pwm power loss (w) 2 3 1 0 5 4 pwm 2.7v in 5v in 12v in loss burst load current (a) 0.0001 efficiency (%) 40 60 10 3118 g08 20 0 0.001 0.01 0.1 1 100 30 50 10 70 80 90 pwm power loss (w) 2 3 1 0 5 4 pwm 2.7v in 5v in 12v in loss burst input voltage (v) 2 efficiency (%) 90 18 3118 g09 80 70 4 12 14 16 6 8 10 100 85 95 75 v in1 , load = 500ma v in2 , load = 500ma v in1 , load = 1a v in2 , load = 1a load current (a) 0 die temperature rise from ambient (c) 40 2.5 3118 g12 20 0 1 1.5 2 0.5 100 30 50 70 60 80 90 10 v in = 2.7v v in = 5v v in = 12v load current (a) 0 die temperature rise from ambient (c) 40 2.5 3118 g11 20 0 1 1.5 2 0.5 100 60 30 50 70 90 80 10 v in = 3.6v v in = 5v v in = 12v load current (a) 0 die temperature rise from ambient (c) 40 2.5 3118 g10 20 0 1 1.5 2 0.5 100 30 50 80 60 70 90 10 v in = 5v v in = 12v v in = 18v ltc 3118 3118f
6 for more information www.linear.com/ltc3118 typical p er f or m ance c harac t eris t ics n-channel mosfet leakage vs die temperature and stand-off voltage normalized n-mosfet resistance vs v cc normalized n-channel mosfet resistance vs die temperature fb program voltage vs temperature v cc vs active v in pwm to burst mode thresholds vs v in maximum load current vs v in in pwm mode inductor overload, average and reverse current limits vs temperature v in1 or v in2 voltage (v) 2 pwm to burst threshold (ma) 280 18 3118 g13 140 0 6 14 16 4 8 1210 420 210 350 70 5v out l = 3.3h 12v out l = 6.8h v in1 or v in2 voltage (v) 2 maximum load current (a) 2.5 18 3118 g14 1.5 0 6 14 16 4 8 1210 3.5 2.0 3.0 1.0 0.5 12v out l = 6.8h 5v out l = 3.3h diode from v out = 5v to v cc temperature (c) ?50 inductor current (a) 1 150 3118 g15 0 ?1 ?10 70 90 110 130 ?30 10 5030 6 2 3 4 5 overload average reverse stand-off voltage (v) 0 leakage current (a) 10 18 3118 g16 0 6 15 3 9 12 1000 1 100 25c 50c 75c 100c 125c 150c 175c v cc voltage (v) 2.5 normalized resistance 1.0 5.5 3118 g17 0.8 0.6 3.53 4 54.5 1.3 0.9 1.1 1.2 0.7 temperature (c) ?50 normalized resistance 1.0 150 3118 g18 0.8 0.6 0 100 50 1.4 1.3 0.9 1.1 1.2 0.7 temperature (c) ?50 fb voltage (v) 1.000 150 3118 g19 0.985 0.975 0 100 50 1.025 1.015 0.990 0.995 1.005 1.010 1.020 0.980 active v in voltage (v) 2 v cc voltage (v) 3.3 18 3118 g20 2.7 2.3 4 6 8 16141210 3.9 2.9 3.1 3.5 3.7 2.5 ltc 3118 3118f
7 for more information www.linear.com/ltc3118 typical p er f or m ance c harac t eris t ics mode and sel logic thresholds active v in in ideal diode mode with hysteresis run1 and run2 thresholds for v in uvlo and v cc enable run1 and run2 current vs voltage sw1, sw2 minimum low time vs v cc v cc vs supply current (v in > 5v) showing current limit no-load active v in current in burst mode no-load active v in current in pwm v cc supply current (ma) 0 v cc voltage (v) 80 3118 g21 3.6 3.4 60 40 20 3.9 3.7 3.8 3.5 active v in voltage (v) 2 quiescent current (a) 125 18 3118 g22 50 0 4 6 8 16141210 250 150 75 100 200 225 175 25 v out = 5v diode from v out = 5v to v cc v out = 12v active v in voltage (v) 2 quiescent current (ma) 20 18 3118 g23 12 0 4 6 8 16141210 24 16 4 8 v out = 12v v out = 5v diode from v out = 5v to v cc temperature (c) ?50 threshold voltage (v) 1.0 150 3118 g24 0.4 0 0 100 50 1.4 0.6 0.8 1.2 0.2 rising falling v in2 voltage (v) 2 v in1 voltage (v) 18 3118 g25 12 2 4 6 8 16141210 18 14 16 10 4 6 8 v in1 active v in2 active sel = v cc temperature (c) ?50 threshold voltage (v) 150 3118 g26 1.0 0 0 50 100 1.4 1.2 0.8 0.2 0.4 0.6 v cc on v cc off v in uvlo rising v in uvlo falling run voltage (v) 0 2 run current (a) 4.5 18 3118 g27 3.0 0 4 6 8 16141210 5.0 3.5 4.0 2.5 1.0 1.5 2.0 0.5 v cc voltage (v) 2.5 3 minimum low time (ns) 5.5 3118 g28 80 3.5 4 4.5 5 160 120 140 100 ltc 3118 3118f
8 for more information www.linear.com/ltc3118 typical p er f or m ance c harac t eris t ics 5v in burst mode waveforms 12v out , 50ma 12v in burst mode waveforms 12v out , 100ma 18v in burst mode waveforms 12v out , 100ma soft-start waveforms with 500ma load (12v in , 12v out ) v out short-circuit waveforms response and recovery (12v in , 12v out ) switch and v out waveforms (12v in , 12v out ) 12v in2 to 5v in1 switchover waveforms, v out = 12v 500ma load 100ma to 1a load step pwm mode (12v in , 12v out ) v cc short-circuit waveforms response and recovery (12v in , 12v out , 500ma load) 200ns/div 3118 g29 12v out ripple 100mv/div i l 1a/div sw1 5v/div sw2 5v/div 500s/div 3118 g30 12v out ac-coupled 500mv/div i l 1a/div sel 5v/div sw1 10v/div l = 6.8h c out = 100f 500s/div 3118 g31 12v out ac-coupled 500mv/div i l 1a/div inductor 1a/div vc 200mv/div l = 6.8h c out = 100f 5s/div 3118 g32 12v out ripple 100mv/div i l 0.5a/div sw2 10v/div sw1 10v/div l = 6.8h c out = 100f 5s/div 3118 g33 12v out ripple 100mv/div i l 0.5a/div sw2 10v/div sw1 10v/div l = 6.8h c out = 100f 5s/div 3118 g34 12v out ripple 100mv/div i l 0.5a/div sw2 10v/div sw1 10v/div l = 6.8h c out = 100f 200s/div 3118 g35 v out 5v/div i l 1a/div vc 500mv/div run1 or run2 5v/div r l = 24 1ms/div 3118 g36 v out 5v/div i l 2a/div vc 500mv/div v out shorted short released 2ms/div 3118 g37 v out 10v/div i l 1a/div v cc 5v/div v cc shorted short released ltc 3118 3118f
9 for more information www.linear.com/ltc3118 p in func t ions sel (pin 1/pin 4): input select pin. sel = logic low ( ground): v in1 priority mode, the con- verter will operate from v in1 if run1 and v in1 voltages are above their respective thresholds. if these conditions are not met, the converter will operate from v in2 as long as run2 and v in2 voltages are above their thresholds. sel = logic high ( connect to v cc ): ideal diode mode, the converter will operate from the higher voltage of v in1 or v in2 . v in1 (pin 2/pin 5): the first input voltage source for the converter. connect a minimum of 22 f ceramic decou- pling capacitor from this pin to ground, as close to the ic as possible. in ideal diode mode (sel = 1), this input will be selected if v in1 > v in2 , v in1 is above its internal uvlo threshold, and run 1 > 1.22 v. in priority mode (sel = 0), this input will be selected if v in1 is above its internal uvlo threshold and run1 > 1.22v. since this input has lower r ds(on) mosfets between v in1 and sw1, it should be considered for use with the source where high efficiency is more critical. run1 (pin 3/pin 6): input to enable and disable the ic and program the uvlo threshold for v in1 . pull run1 above 1.22v to enable the converter. connecting this pin to a resistor divider from v in1 to ground allows programming of v in1 s uvlo threshold above 2.2 v. pulling both run1 and run2 to logic low states will put the ic in a low cur- rent shutdown state. run 2 ( pin 4/pin 7): input to enable and disable the ic and program the uvlo threshold for v in2 . pull run2 above 1.22v to enable the converter. connecting this pin to a resistor divider from v in2 to ground allows programming of v in2 s uvlo threshold above 2.2 v. pulling both run1 and run2 to logic low states will put the ic in a low cur- rent shutdown state. v cc ( pin 5/ pin 8): output voltage of the internal v cc regula - tor. this is the supply pin for the internal driver circuitry. bypass this output with a 4.7 f ceramic capacitor. this pin may be back driven by an external supply, up to 5.5v. v cc will be generated from either v in1 or v in2 depending upon which input the converter is operating from. mode (pin 6/ pin 9): pwm or auto burst mode select pin. mode = logic low ( ground): enables automatic burst mode operation. mode = logic high ( connect to v cc ): forces pwm mode operation. gnd (pin 7/pins 10, 11): signal ground for the ic. provide a short direct pcb path from this pin to the ground plane. vc (pin 8/pin 12): output of the voltage error amplifier used to program average inductor current. an rc from this pin to ground sets the voltage loop compensation. the average current loop is internally compensated. fb (pin 9/pin 13): feedback input to the voltage error am - plifier. connect to a resistor divider from v out to ground. the output voltage can be adjusted from 2 v to 18 v by: v out = 1 + (r1/r2). v1gd (pin 10/pin 14): open-drain indicator that pulls to ground when both v in1 and run1 are above their respec- tive thresholds . connect a pull-up resistor from this pin to a positive supply. v2gd (pin 11/pin 15): open-drain indicator that pulls to ground when both v in2 and run2 are above their respec- tive thresholds . connect a pull-up resistor from this pin to a positive supply. pgd (pin 12/pin 16): open-drain output that pulls to ground when v out is greater than 92% of the programmed output voltage. connect a pull-up resistor from this pin to a positive supply. v out (pin 13/pin 19): regulated output voltage. con- nect a minimum of 47 f ceramic or low esr decoupling capacitor from this pin to ground. the capacitor should be placed as close to the ic as possible with short, wide traces to v out and gnd. sw2 (pin 14/pin 20): switch pin. connect to the other side of the inductor. keep pcb trace lengths as short and wide as possible to reduce emi. bst2 (pin 15/pin 21): bootstrapped floating supply for high side n-channel mosfet gate drive. connect to sw2 through a 0.1 f capacitor, as close to the part as possible. (qfn/tssop) ltc 3118 3118f
10 for more information www.linear.com/ltc3118 p in func t ions (qfn/tssop) bst1 (pin 16/pin 22): bootstrapped floating supply for high side n-channel mosfet gate drive for v in1 or v in2 . connect to sw1 through a 0.1 f capacitor, as close to the part as possible. this capacitor provides gate drive for the n-channel mosfets connected between sw1 and either v in1 or v in2 . sw1 (pin 17/pin 23): switch pin. connect to one side of the inductor. keep pcb trace lengths as short and wide as possible to reduce emi. v in2 (pin 18/pin 24): the second input voltage source for the converter. connect a minimum of 22 f ceramic decou - pling capacitor from this pin to ground, as close to the ic as possible. in ideal diode mode (sel = 1), this input will be selected if v in2 > v in1 , v in2 is above its internal uvlo threshold, and run 2 > 1.22 v. in priority mode (sel = 0), this input will only be selected if v in1 is below its internal uvlo threshold or run1 < 1.05v. since this input has the higher r ds(on) mosfets between v in2 and sw1, it should be considered for use with the source where slightly lower conversion efficiency is ac- ceptable. cp 2 ( pin 19/ pin 25): positive pin for the v in2 top n- channel mosfet charge- pump capacitor. this pin toggles between v in2 and v in2 + v cc when v in2 is active. cn2 (pin 20/pin 27): negative pin for the v in2 top n-channel mosfet charge-pump capacitor. this pin is driven between v cc and gnd when v in2 is active. connect a 10 nf ceramic capacitor between cn2 and cp2. this pin can be monitored to indicate operation from v in2 . cm 2 (pin 21/pin 28): filter pin for the common connec- tion of v in2 to sw1 n-channel mosfets. connect a 47 nf capacitor from this pin to the ground plane. cm1 (pin 22/pin 1): filter pin for the common connec - tion of v in1 to sw1 n-channel mosfets. connect a 47 nf capacitor from this pin to the ground plane. cn 1 ( pin 23/ pin 2): negative pin for the v in 1 top n- channel mosfet charge-pump capacitor. this pin is driven be- tween v cc and gnd when v in1 is active. connect a 10nf ceramic capacitor between cn1 and cp1. this pin can be monitored to indicate operation from v in1 . cp 1 (pin 24/pin 3): positive pin for the v in1 top n-channel mosfet charge - pump capacitor. this pin toggles between v in1 and v in1 + v cc when v in1 is active. pgnd ( exposed pad pin 25/pins 17, 18, 26, exposed pad pin 29): power ground for the ic. the exposed pad must be soldered to the pcb ground plane. it serves as the power ground connection, and as a means of conducting heat away from the die. ltc 3118 3118f
11 for more information www.linear.com/ltc3118 b lock diagra m + ? + ? + ? + ? + ? + ? v cc v cc v cc v in2 fb 0.92v v in1 v in2 2v v cc 2.35v 6a v in2 pgd v in1 v cc v cc 1v i sense r cs 1.2mhz ramps/ oscillator soft-start ramp 3118 bd i swa i swb cm1 cm2 pgnd b d c l v in2 v in1 v in2 2.2v to 18v v out 2v to 18v 2.2v to 18v bst1 bst2 v in1 sw1 sw2 v out 3.8v regulator 1.22v reference cp2 cn2 cp1 cn1 + ? v cc vc fb r1 r2 sel run1 run2 mode gnd v1gd v2gd v in1good pwm comparator average current amplifier 1.22v v in2good run/sd v select run burst switch commands uvlo drivers adrv bdrv cdrv ddrv ideal diode mode up to 18v v1 priority mode v in1good v in1goo2 i sense i sense i swa i swb clk sel2 pmp2 v in1 v cc clk sel1 pmp1 + ? g m + ? bdrv cp1 cp2 + ? ? + i peak ddrv cdrv i rev a fets and drivers ?200ma c out ltc 3118 3118f
12 for more information www.linear.com/ltc3118 o pera t ion introduction the ltc3118 is a dual-input, current mode, monolithic buck-boost dc/dc converter that can operate over a wide input voltage range of 2.2 v to 18 v. the output voltage can be programmed between 2 v to 18 v and deliver more than 2 a of load current. the ltc3118 operates from either v in1 or v in2 depending on the state of the sel pin. if sel is commanded to be a logic high, v out will be powered from the highest valid input voltage. if sel is a logic low, v out will be powered from v in1 ( priority mode) assuming sufficient input voltage is present. internal, low r ds(on) n-channel power switches reduce the solution complexity and maximize efficiency. a proprietary switch algorithm allows the buck-boost converter to maintain output voltage regulation with in - put voltages that are above, below or equal to the output voltage. transitions between the step-up or step-down operating modes are seamless and free of transients and subharmonic switching, making this product ideal for noise sensitive applications. the ltc3118 operates at a fixed nominal switching frequency of 1.2mhz, which provides an ideal trade-off between small solution size and high efficiency. current mode control provides inherent input line voltage rejection, simplified compensation and rapid response to load transients. burst mode operation capabil - ity is also included in the ltc3118 and is user-selected via the mode input pin. in burst mode operation, the ltc3118 provides exceptional efficiency at light output loads by operating the converter only when necessary to maintain voltage regulation. at higher loads, the ltc3118 automatically transitions to fixed frequency pwm mode when burst mode operation is selected. for 5 v v out applications, the input quiescent currents in burst mode operation can be reduced with the internal ldo regulator bootstrapped to the output voltage. if the application requires extremely low noise, continuous pwm operation can also be selected via the mode pin. the ltc3118 also features accurate, resistor programmable run comparator thresholds with hysteresis for each v in . this allows the buck-boost dc/dc converter to turn on and off at user-selected voltage thresholds depending on the power source for each v in . with a wide voltage range and high efficiency, the ltc3118 is well suited for many demanding power systems. power stage topology figure 1 shows the topology of the dual-input ltc3118 power stage switches and their associated gate drivers. the ltc3118 integrates independent switch paths from v in1 to sw1 and v in2 to sw1 to provide isolation between the selected input and the inactive input. this configuration allows conversion from either input source, regardless of their respective voltage levels, enabling ideal diode or v in1 priority modes (see sel pin description). figure 1. ltc3118 dual - input power stage 3118 f01 v in1 v out v cc v cc pump1 a1 on bst1 a1 cm1 v in2 a2 on sw1 sw2 bst1 a2 cm2 bst2 l pgnd b c d b on c on d on pump2 ltc 3118 3118f
13 for more information www.linear.com/ltc3118 o pera t ion if operation from v in1 is selected, pump1 connects the low r dson static switch between v in1 and cm1 as shown. switch a1 is then driven on for a portion of each switching cycle, as commanded by the pwm circuitry and powered by the flying capacitor between bst1 and sw1. when operating from v in1 , pump2 and a2 are disabled. operation from v in2 is accomplished in a similar man- ner, except that pump2 connects v in2 to cm2 and a2 is commanded on by the pwm . with operation from v in2 , pump1 and a1 are disabled providing isolation from v in1 . pwm mode operation if the mode pin is high, or if the load current on the converter is high enough to force pwm mode operation, the ltc3118 operates at a fixed 1.2 mhz frequency us - ing a current mode control loop. pw m mode minimizes output voltage ripple and yields a low noise switching frequency spectrum. a proprietary switching algorithm provides seamless transitions between operating modes and eliminates discontinuities in the average inductor current, inductor ripple current and loop transfer function throughout all modes of operation. these advantages result in increased efficiency, improved loop stability and lower output voltage ripple . in pwm mode operation, both sw1 and sw2 transition on every cycle independent of the input and output voltages. in response to the internal control loop command, an internal pulse width modulator generates the appropriate switch duty cycle to maintain regulation of the output voltage. when stepping down from a high input voltage to a lower output voltage, the converter operates in buck mode and switch d remains on for the entire switching cycle except for a minimum sw2 low duration (typically 100 ns). dur - ing the switch low duration, switch c is turned on which for ces sw2 low and charges the flying capacitor between bst2 and sw2. this ensures that the switch d gate driver power supply rail on bst2 is maintained. the duty cycle of switch a 1 ( or a2) and switch b are adjusted by the pwm circuit to maintain output voltage regulation in buck mode. if the input voltage is lower than the output voltage, the converter operates in boost mode. switch a 1 ( or a2) remains on for the entire switching cycle except for the minimum switch low duration ( typically 100 ns). during the switch low duration, switch b is turned on which forces sw1 low and charges the flying capacitor between bst1 and sw1. this ensures that switch a 1 ( or a2) gate driver power supply rail on bst1 is maintained. the duty cycle of switch c and switch d are adjusted by the pwm circuit to maintain output voltage regulation in boost mode. oscillator the ltc3118 operates from an internal oscillator with a nominal fixed frequency of 1.2 mhz. this allows the dc/dc converter efficiency to be maximized while still using small external components. input select logic and v in power good indicators a simplified schematic diagram of the ltc3118s input select circuitry is shown in figure 2. uvlo comparators on v in1 , v in2 and v cc set minimum operating voltages to ensure proper operation. v cc must be greater than 2.35v before operation is allowed from either input. once v cc is valid, one of the inputs must be greater than 2 v typical before the ltc3118 enables switching. finally, the run pin voltage for the particular input must be greater than 1.22v to enable operation. this condition will be met if the appropriate run pin is connected to its own v in , run1 to v in1 for example, but may not be met if a resistor divider is used to program the accurate run pin higher than the v in uvlo minimum. detailed discussions of v cc , v in and run pin uvlos are presented in later sections. once the uvlo conditions are satisfied, internal v in1good and/or v in2good will assert and the ltc3118 is allowed to operate. the state of each v ingood signal and the sel pin are decoded in logic to determine which input source is selected, as shown on the table in figure 2. open-drain indicator pins v1gd and v2gd are driven by their respective internal v ingood signals and can be used to alert the system of undervoltage conditions on the inputs. external pull-up resistors can be connected between these pins and any supply voltage up to 18v. since these pins pull low with valid input voltages, even in burst mode operation, high value resistors are recom - mended for applications where minimal no-load quiescent current is critical. ltc 3118 3118f
14 for more information www.linear.com/ltc3118 o pera t ion if sel is a logic low, the ltc3118 operates in v in1 priority mode where v in1 is selected for operation if conditions are met for v in1good to be high. if v in1good is low in priority mode, the ltc3118 will revert to v in2 operation if v in2(good) is asserted, keeping v out powered. if sel is a logic high, the ltc3118 operates in ideal diode mode, where v out is powered from the highest input voltage source with a high v ingood signal. an internal comparator with 400 mv hysteresis monitors the input voltages to determine which is higher. if the state of this comparator changes during pwm operation, switching will be suspended for six clock cycles before resuming from the other input source. an approximate 250 s filter/ time constant prevents rapid transitions between inputs. as with priority mode, if one of the v ingood signals is low the ltc3118 will operate from the other input in order to keep the output powered. if both v ingood signals are low in either mode, the ltc3118 will not deliver power to v out . v out power good indicator the v out power good indicator is an open-drain output pin similar to the v1gd and v2gd pins shown in figure 2. pgd is driven by an internal comparator that monitors the fb pin. if fb is below 0.92v (v out is 8% low) pgd will open circuit, allowing an external resistor to pull high indicating the output voltage is not in regulation. the power good comparator has internal filtering for glitch suppression. figure 2. simplified input select logic and v in power good indicators 3118 f02 + ? 2v v in2 v2gd + ? 1.22v run2 + ? 1.22v run1 v1gd + ? 2v v in1 + ? 2.35v v cc v ccgood v in2good v in1good uvlo comparators input voltage select logic sel pin v in1good v in2good selected v in 1 ideal diode mode 1 1 highest v in 1 0 v in1 0 1 v in2 0 0 no switching 0 priority mode 1 1 v in1 1 0 v in1 0 1 v in2 0 0 no switching ltc 3118 3118f
15 for more information www.linear.com/ltc3118 o pera t ion current mode control the ltc3118 utilizes average current mode control for the pulse width modulator, as shown in figure 3. current mode control, both average and the better known peak method, enjoy some benefits compared to other control methods, including: simplified loop compensation, rapid response to load transients and inherent line voltage rejection. referring to figure 3, an internal high gain transcon - ductance error amplifier, labeled v amp , monitors v out through a voltage divider connected to the fb pin and provides an output, vc, used by the current mode control loop to command the appropriate inductor current level. to ensure stability, external frequency compensation components (r z , c p1 and c p2 ) must be installed be- tween vc and gnd. the procedure for determining these components is provided in the applications information section of this data sheet. vc is internally connected to the noninverting input of a high gain, integrating, operational amplifier, referred to in figure 3 as i amp . the inverting input of the average current amplifier is connected to the inductor current sense resistor r cs through a gain-setting resistor r a1 and to its output (i comp ) through an internal frequency compensation network comprised of r a2 and c a . the average current amplifiers output provides the cycle-by-cycle duty cycle command into the buck-boost pwm circuitry. the non-inverting reference level input to the average current amplifier is vc and the feedback or inverting input is driven from the inductor current sensing circuitry. the inductor current sensing circuitry alternately measures the current through switches a 1 ( or a2) and b. the output of the sensing circuitry produces a voltage across resistor r cs that resembles the inductor current waveform transformed to a voltage. if there is an increase in the power converter load on v out , the instantaneous level of v out will drop slightly, which will increase the voltage level on vc by the inverting action of the voltage error amplifier. when the increase on vc first occurs, the output of the current averaging amplifier, i comp , will increase momentarily to command a larger duty cycle. this duty cycle increase will result in a higher inductor current level, ultimately raising the average voltage across r cs . once the average figure 3. average current mode control loop 3118 f03 v out 1v 1.2mhz ramps/ oscillator to switches i l i comp sw1 sw2 r a1 r a2 c a inductor current sense vc c p1 c p2 + ? fb i amp v amp r cs r1 r2 r z i avg pwm drive logic ? + ltc 3118 3118f
16 for more information www.linear.com/ltc3118 o pera t ion value of the voltage on r cs is equivalent to the vc level, the voltage on i comp will revert very closely to its previ- ous level into the pw m , and force the correct duty cycle to maintain voltage regulation at this new higher inductor current level. the average current amplifier is configured as an integrator, so in steady state, the average value of the voltage applied to its inverting input ( voltage across r cs ) will be equivalent to the voltage on its noninverting input vc. as a result, the average value of the inductor current is controlled in order to maintain voltage regulation. the entire current amplifier and pwm can be simplified as a voltage controlled current source, with the driving volt - age coming from vc. vc is commonly referred to as the current command for this reason, and the voltage on vc is directly proportional to average inductor current, which can prove useful for many applications. the voltage error amplifier monitors v out through a voltage divider and makes adjustments to the current command as necessary to maintain regulation. the voltage error amplifier therefore controls the outer voltage regulation loop. the average current amplifier makes adjustments to the inductor current as directed by the voltage error amplifier output via vc and is commonly referred to as the inner current loop amplifier. the average current mode control technique is similar to peak current mode control except that the average current amplifier, by virtue of its configuration as an integrator, controls average current instead of the peak current. this difference eliminates the peak-to-average current error inherent to peak current mode control, while maintaining most of the advantages inherent to peak current mode control. average current mode control requires appropriate compensation for the inner current loop, unlike peak current mode control. the compensation network must have high dc gain to minimize v out regulation errors and high bandwidth to quickly change the commanded current level following transient load steps. the inner loop compensation components are fixed internally on the ltc3118. external compensation of the voltage loop is detailed in the applications information section and is similar to techniques used for peak current mode control. inductor current sense and maximum output current as part of the current control loop, the ltc3118 has cur - rent sense circuitry that measures the inductor current of the buck-boost converter, as shown in figure 3. this cir cuitr y measures the current through switches a 1 (or a2) and b separately and produces proportional output currents that are summed at the current sense resistor r cs . sensed a and b switch currents form a voltage replica of the inductor current at r cs , which is used by the average current amplifier, as described in the previous section. the voltage amplifier output, vc, is internally clamped to a nominal value of 1 v. since the average inductor current is proportional to vc, the 1 v clamp sets the maximum average inductor current that can be programmed by the inner current loop. taking into account the current sense amplifier s gain, and the value of r cs , the maximum average inductor current is 3.6 a typical. in buck mode, the output current is approximately equal to the inductor current i l . i out(buck) i l ? 0.85 the 100 ns sw1/sw2 forced low time on each switching cycle briefly disconnects the inductor from v out and v in , resulting in slightly less output current in either buck or boost mode for a given inductor current. in boost mode, the output current is related to average inductor current and duty cycle by: i out(boost) i l ? (1 C d) where d is the converter duty cycle. since the output current in boost mode is reduced by the duty cycle ( d), the output current rating in buck mode is always greater than in boost mode. also, because boost mode operation requires a higher inductor current for a given output current compared to buck mode, the efficiency in boost mode will be lower due to higher conduction (i l 2 ? r ds(on) ) losses in the power switches. this will fur- ther reduce the output current capability in boost mode. in ei ther operating mode, however, the inductor peak - to- peak ripple current does not play a major role in determining the output current capability. ltc 3118 3118f
17 for more information www.linear.com/ltc3118 o pera t ion the maximum load current capability in pwm mode curves in the typical performance characteristics section show the relationship of input voltage and the ability to deliver load current at v out = 5 v and 12 v. when the input voltage is a volt or more above v out in buck mode, the ltc3118 is capable of providing more than 2 a of load current. in boost mode, the output current capability is further reduced by the boost ratio or duty cycle ( d) as described in the preceding equation. overload current limit and reverse current comparators the internal current sense waveforms are used by the peak overload current (i peak ) and reverse current (i rev ) comparators. the i peak current comparator monitors i sense and interrupts normal pwm operation if the induc- tor current level exceeds its maximum internal threshold. this threshold is approximately 60% above the maximum average current level of the current control loop. if the internal current sense waveform rises above this level, the ltc3118 will disconnect the inductor from v in by shut- ting off switch a 1 ( or a2) to prevent higher current in the inductor. the i peak circuitry is reset by the oscillator clock at the end of each switching cycle. in the event that the overload comparator is tripped as the result of an output short-circuit condition, where v out is discharged below approximately 1 v, the ltc3118 will initiate a soft-start event keeping the on-chip power dissipation to low levels. once the short circuit is removed, the ltc3118 will restart in the normal fashion. if the average current loop is able to prevent inductor current from reaching i peak during a short-circuit event, soft-start will not be initiated, but the maximum current capability of the current loop will be reduced by 40% to reduce power dissipation. the ltc3118 contains a reverse current comparator set to a nominal value of C200ma. if the internal current sense waveform transitions below the internally set reverse cur - rent threshold , the ltc3118 will disconnect the inductor from v out by shutting off switch d, to prevent rapid dis- charge of the output capacitor. the i rev circuitry is reset by the oscillator clock at the end of the switching cycle. burst mode operation when the mode pin is held low, the ltc3118 is configured for automatic burst mode operation. as a result, the buck- boost dc/ dc converter will operate with normal continuous pw m switching above a predetermined average inductor current and will automatically transition to power saving burst mode operation below this level. refer to the typical performance characteristics section of this data sheet to determine the burst mode transition threshold for various combinations of v in and v out . with mode held low at light output loads, the ltc3118 will go into a standby or sleep state when the output volt - age achieves its nominal regulation level. the sleep state halts pwm switching and powers down all nonessential functions of the ic, significantly reducing the quiescent current of the ltc3118. this greatly improves overall power conversion efficiency when the output load is light. since the converter does not operate in sleep, the output voltage will slowly decay at a rate determined by the output load resistance and the output capacitor value. when the output voltage has decayed by a small amount, the ltc3118 will wake up and resume normal pwm switching operation until the voltage on v out is restored to the previous level. if the load is very light, the ltc3118 may only need to switch for a few cycles to restore v out , and may sleep for extended periods of time, significantly improving conversion efficiency. ltc 3118 3118f
18 for more information www.linear.com/ltc3118 soft-start the ltc3118 soft-start circuit minimizes inrush current and output voltage overshoot on initial power up. the required timing components for soft-start are internal to the ltc3118 and produce typical soft-start durations of approximately 1 ms. the internal soft-start circuit slowly ramps the error amplifier output at vc. in doing so, the current command of the ic is slowly increased, starting from zero. after initial power-up, soft-start can be reset by uvlo on v cc , both v in1good and v in2good de-asserting, thermal shutdown, or a v out short circuit. v cc regulator an internal low dropout regulator ( ldo) generates a nominal 3.8 v rail from the active input v in1 or v in2 . the v cc rail powers the internal control circuitry and power device gate drivers of the ltc3118, including the bst pin capacitors. the v cc regulator is disabled in shutdown to reduce quiescent current and is enabled by forcing one run pin above its logic threshold. the v cc regulator includes current-limit protection to safeguard against accidental short-circuiting of the ldo rail. in 5 v v out ap- plications, v cc can be powered by v out through an external schottky diode. this technique is commonly referred to as bootstrapping. bootstrapping can provide a significant efficiency improvement, particularly when the active v in is high, and also allows operation to the minimum rated input voltage of 2 v. for more information see bootstrap - ping the v cc regulator with 5 v v out or external supply, in the applications information section. undervoltage lockouts the ltc3118 undervoltage lockout ( uvlo) circuits disable operation of the internal power switches if both v in1 and v in2 or the v cc voltages are below their respective uvlo thresholds ( see figure 2). there are three uvlo circuits, one for each v in and another that monitors v cc . the v in uvlo comparators have a falling voltage threshold of 1.8v (typical at room temperature). if both input voltages fall below this level, switching is disabled until one v in rises above 2 v, as long as v cc is above its uvlo threshold. the v cc uvlo has a falling voltage threshold of 2.2v (typical). if v cc falls below this threshold, ic operation is disabled until v cc rises above 2.35 v as long as one v in is above its uvlo threshold level. depending on the particular application, any of these uvlo thresholds could be the limiting factor affecting the minimum input voltage required for operation. the ltc3118 v cc regulator uses v in1 or v in2 for its power input, whichever is active ( see the input select logic and v in power good indicators section). if v cc is not boot- strapped, there exists a voltage drop between the active v in and v cc . the dropout voltage is proportional to the loading on v cc due to the gate charge to the internal power switches. the typical performance characteristics section of this data sheet provides information on the dropout voltage between v in1 (or v in2 ) and v cc . in applications where v cc is bootstrapped ( powered by v out through a schottky diode or auxiliary power rail), the minimum input voltage for operation ( after start-up) will be limited only by the v in uvlo thresholds (1.8v typical). please note: if the bootstrap voltage is derived from the ltc3118 v out and not an independent power rail, then the minimum input voltages required for initial start-up are still limited by the minimum v cc voltage (2.35v typical). o pera t ion ltc 3118 3118f
19 for more information www.linear.com/ltc3118 run1 and run2 pin comparators forcing both run1 and run2 to a logic low places the ltc3118 in a low current shutdown state. when the volt - age on either pin is brought above a 0.65 v logic threshold, certain ic functions are enabled as shown in figure 4a. the run1 and run2 pins also include accurate internal comparators that allow them to be used to set custom rising and falling on/off thresholds for v in1 and v in2 , respectively, with the addition of external resistor dividers. if either run pin voltage is increased to exceed its accurate comparator threshold (1.22 v nominal), all functions of the buck-boost converter will be enabled and switching will commence, assuming the respective v in and v cc uvlo circuits are cleared (see figure 2). if both run1 and run2 are brought below the accurate comparator threshold, the buck- boost converter will inhibit switching, but the v cc regulator and control circuitry will remain powered unless both run pins are brought below the logic threshold. therefore, in order to completely shut down the ic and reduce the v in currents to < 2a (typical), it is necessary to ensure that both run pins are brought below the worst -case low logic threshold of 0.2v. run1 and run2 are high voltage capable inputs but must be connected to their respective v in1 and v in2 supplies through a high value resistor greater than 200 k to prevent a potential latch condition at the pin. the run pins can be driven above v in or v out within their specified voltage ratings. if either run pin is forced above 5 v, it will sink a small current, as given by the following equation: i run v run ? 5v 3m with the addition of optional resistor divider(s), as shown in figure 4 a, the run pin(s) can be used to establish a user-programmable turn-on and turn-off threshold. the buck-boost converter is enabled when the voltage on either run pin reaches 1.22 v. therefore, the turn-on voltage threshold on v in is given by: v turnon = 1.22v 1 + r t r b ? ? ? ? ? ? figure 4. (a) accurate run1 or run2 pin comparators, (b) manual v in select with overlap timing, (c) active v in indicators o pera t ion 1.22v v in ltc3118 3118 f04a run1 or run2 r t r b enable switching logic threshold accurate threshold enable ldo and control circuits + ? 0.65v + ? (a) (b) (c) 3118 f04b 1m logic signal logic signal 100pf run1 1m 100pf run2 v in1 v in2 v in1 v in2 3118 f04c 1m 100pf v in1 active v in2 active cn1 1m 100pf cn2 ltc 3118 3118f
20 for more information www.linear.com/ltc3118 the run comparators include a built-in hysteresis of approximately 170mv, so that the turn-off threshold will be approximately 15% lower than the turn-on threshold. put another way, the internal threshold levels for the run comparators to disable switching from a particular input is 1.05v. v turnoff = 1.05v 1 + r t r b ? ? ? ? ? ? the run comparator is relatively noise insensitive, but there may be cases due to pcb layout, very large value resistors for r t and r b (figure 4 a), or proximity to noisy components where noise pickup is unavoidable and may cause the turn-on or turn-off levels to be intermittent. in these cases, a small value filter capacitor can be added across r b to ensure proper operation. selecting priority or ideal diode mode operation priority mode (sel=0) priority mode operation is suggested for most applications, since powering from one of the sources is typically preferred. in priority mode, the primary input is connected to v in1 and the auxiliary input is connected to v in2 . the ltc3118 will maintain operation from v in1 until either the run1 or minimum v in1 uvlo circuits transition the ltc3118 to v in2 operation if valid. it is important that the run1 turn-off threshold programs the minimum v in1 above 2.5 v in priority mode unless v cc is back-fed and held above 2.5 v. this prevents an unintended soft-start cycle from occurring if v cc hits its uvlo threshold when the v in1 source is removed, before transitioning to v in2 operation. depending on the maximum load current of the application , the run1 and run2 minimum v in turn-off thresholds may need to set well above 2.5 v to prevent v out from losing regulation, especially in step-up mode. please refer to maximum load current vs v in curves found in the typical performance characteristics. maximum load current capability when v in1 or v in2 is less than 3.8 v can be improved if v cc is boot-strapped to 5 v as shown in figure 7. ideal diode mode (sel=1) ideal diode mode operation is available on the ltc3118 for systems with low esr sources or where the programmed operating range of the two inputs can be separated as will be discussed. in ideal diode mode, an internal comparator monitors the voltage on both v in1 and v in2 to determine which input is higher. the comparator has approximately 800mv of hysteresis to help prevent the part from switching between the two inputs if the source voltages are equal. the comparator has an approximate 250 s filter delay to prevent rapid switching between inputs and erratic operation. when the ltc3118 switches between inputs, current supplied from one source is suspended before transitioning to the other source. depending on the impedance of each source and the amount of input current required to support the load on v out , it is possible for the voltage ripple on one or both inputs to exceed this comparators hysteresis. as an example, if both input sources have 300 m of impedance and 2 a of current is being drawn from the active source, a 600 mv step will occur on the inputs during switchover, approaching the comparators 800mv of typical hysteresis. when the input voltages are equal, the ltc3118 could toggle between v in1 and v in2 operation at high load currents. for such systems, operation in priority mode is recommended, unless the run pins can be programmed such that the minimum operating voltage of one input is set above the maximum source voltage of the other input. as with priority mode, the minimum v in operating voltages should be set by their run pins above v cc uvlo and higher if needed to support maximum load current. low esr 100 f to 220 f aluminum electrolytic capacitors close to both input pins help to reduce resonant ringing during v in switchover, due to cable inductances found in some applications and bench evaluation set-ups . o pera t ion ltc 3118 3118f
21 for more information www.linear.com/ltc3118 o pera t ion manual v in select circuits the sel pin can be used to manually switch between v in1 and v in2 , if v in2 is connected to a voltage greater than v in1 . in this case, both run pins must remain asserted above their 1.22 v thresholds. the ltc3118 will run off v in1 when sel is low and the higher v in2 source when sel is high. for systems requiring manual v in selection where the relative voltages are unknown, the run pins can be used with a few precautions. each run pin contains internal filtering to reduce the chance of unintended turn-on or turn-off due to noise events. the turn-on delay is typically 50s in order to manage inductive ringing during supply plug in. accordingly, a >100 s overlap time of asserted run1 and run2 signals is recommended to prevent a momentary shutdown of the ic and a subsequent soft- start cycle. if this overlap timing cannot be provided by the system micro-controller, an external circuit similar to figure 4b can be added to each run pin. with the added circuit, v in1 and v in2 can be driven alternately off and on as shown. the diode provides a faster turn-on path, where the rc delay to gnd is set to ~100 s in order to prevent v out from drooping during switch-over. active v in indicator the v1gd and v2gd indicators can be monitored to determine if v in1 or v in2 have sufficient voltage based on internal uvlo circuits and the run pin divider networks as previously discussed. some applications may require an additional indication of which v in is active and which is inactive. this indication can be implemented with the cn1 and cn2 charge-pump pins and an external circuit similar to figure 4 c. the diode and rc network provide peak detection and filtering of the active cn pin which is switching in pwm mode and held high in sleep. the cn pin for the inactive v in is held low. thermal considerations the power switches of the ltc3118 are designed to oper- ate continuously with currents up to the internal current limit thresholds. however, when operating at high current levels, there may be significant heat generated within the ic. in addition, the v cc regulator can generate a significant amount of heat when the active v in is high. this adds to the total power dissipation of the ic. as described elsewhere in this data sheet, bootstrapping of v cc for 5 v output ap- plications can essentially eliminate this power dissipation term and significantly improve efficiency. careful consideration must be given to the thermal envi - ronment of the ic in order to provide a means to remove heat from the ic and ensure that the ltc3118 is able to provide its full rated output current. specifically, the exposed die attach pad of both the qfn and fe packages must be soldered to a copper layer on the pcb to maximize the conduction of heat out of the ic package. this can be accomplished by utilizing multiple vias from the die attach pad connection underneath the ic package to other pcb layer(s) containing large copper planes. a recommended board layout incorporating these concepts is shown in figure 5. typical temperature rise versus load current curves using the pcb in figure 5 are given in the typical performance characteristics section. if the ic die temperature exceeds approximately 165c, thermal shutdown will be invoked and all switching will be inhibited. the part will remain disabled until the die temperature cools by approximately 10 c, at which time a soft-start is initiated to provide a smooth recover y. a pplica t ions i n f or m a t ion ltc 3118 3118f
22 for more information www.linear.com/ltc3118 figure 5. typical 4-layer pc board layout top layer 2nd layer 3rd layer bottom layer ( top view) a pplica t ions i n f or m a t ion ltc 3118 3118f
23 for more information www.linear.com/ltc3118 a pplica t ions i n f or m a t ion figure 6. inactive v in current vs voltage and inductor current (i l ) active v in = v out = 12v in pwm mode inactive input voltage (v) 0 current into inactive input (a) 60 18 3118 f06 20 ?20 3 15 6 9 12 100 40 80 0 i l = 0a i l = 0.5a i l = 1a i l = 2a inactive v in leakage currents the inactive input (v in1 or v in2 ) consumes a small amount of bias current and will exhibit some amount of leakage current, through the disabled switches, depending on the temperature of the die and the average dc voltage between the inactive v in and sw1 (stand- off voltage). please refer to the die temperature rise and n-channel mosfet leakage curves in the typical performance characteristics of the data sheet. the stand- off voltage can be positive or negative depending on the v in1 and v in2 voltages and varies with sw1 duty cycle. figure 6 shows typical currents into the inactive input as a function of its voltage at various levels of inductor current as the ltc3118 operates in pwm mode from an active 12 v input and 12 v output. higher inductor currents generally translate to higher leakage currents due to power dissipation, resulting in a die temperature rise. referring to the curves in figure 6, leakage currents are generally supplied from the inactive source into its re - spective v in pin above a few volts. at lower voltages, it is possible to get reverse current back-fed into the source, causing a depleted battery or unplugged input to slowly charge. in some cases, a dummy load resistor across the inactive input may be needed to prevent that input from rising above its uvlo causing a momentary turn-on. a good thermal design will help to reduce unwanted leakage currents into or out of the inactive input, especially at high switch currents where die temperatures increase. a tight board layout near the v in1 /cm1 and v in2 /cm2 pins to ground is advised to reduce leakage that may occur due to sw1 edge rates and parasitic inductances in the traces . ltc 3118 3118f
24 for more information www.linear.com/ltc3118 a pplica t ions i n f or m a t ion figure 7. bootstrapping v cc a standard application circuit for the ltc3118 is shown on the front page of this data sheet. the appropriate selection of external components is dependent upon the required performance of the ic in each particular application, given considerations and trade-offs such as pcb area, input and output voltage range, output voltage ripple, required efficiency, thermal considerations and cost. this section of the data sheet provides some basic guidelines and con - siderations to aid in the selection of external components and the design of the applications circuit. v cc capacitor selection v cc is generated by a low dropout linear regulator from either v in1 or v in2 , whichever is selected. both v cc regula- tors have been designed for stable operation with a wide range of output capacitors. for most applications, a low esr capacitor of 4.7 f should be used. the capacitor should be located as close to v cc as possible and con- nected to ground through the shortest trace possible. if the connecting trace cannot be made short, an additional 0.1f bypass capacitor should be connected between v cc and ground, as close to the package pins as possible. bootstrapping the v cc regulator with 5v v out or external supply the high and low side gate drivers are powered by v cc , which is generated from the selected v in through an internal linear regulator. in some applications, especially at high input voltages, the power dissipation in the linear regulator can become a significant contributor to thermal heating of the ic. the typical performance characteristics section of this data sheet provides data on v cc current in v out 4.7f 3118 f07 v out ltc3118 v cc pwm operation, which is supplied by v in . a significant performance advantage can be attained in applications where v out is programmed to 5 v, if v cc is powered by v out rather than the selected v in . this can be done by connecting a schottky diode from v out to v cc , as shown in figure 7. with the bootstrap diode installed, the gate driver currents are supplied by the buck-boost converter at high efficiency rather than through the less efficient internal linear regulator. the internal linear regulator contains reverse blocking circuitry that allows v cc to be driven slightly above their nominal regulation level with only a slight amount of reverse current. please note that the bootstrapping supply ( either v out or a separate regulator) must limit v cc to less than 6v. bst, charge pump and cm capacitor selection small ceramic capacitors are needed to provide a suf - ficient amount of charge to the high side switches. as shown in the applications circuits and the front page of this data sheet, small capacitors are required from bst1 to sw1, bst2 to sw2, cn1 to cp1, cn2 to cp2, cm1 to gnd and cm2 to gnd. recommended initial values for the bst to sw capacitors are 0.1 f with > 5 v rating, cn to cp capacitors are 10 nf with > 20 v rating, and cm to gnd capacitors are 47nf with > 20v rating. inductor selection the choice of inductor used in ltc3118 applications influences the maximum deliverable output current, the converter bandwidth, the magnitude of the inductor current ripple and the overall converter efficiency. the inductor must have a low dc series resistance and high output ltc 3118 3118f
25 for more information www.linear.com/ltc3118 current capability or efficiency will be compromised. larger inductor values reduce inductor current ripple, but will not increase output current capability as is the case with peak current mode control, as described in the inductor current sense and maximum output current section of this data sheet. larger value inductors also tend to have a higher dc series resistance for a given case size, which will have a negative impact on efficiency. larger values of inductance also lower the right half plane ( rhp) zero frequency when operating in boost mode, requiring the converter bandwidth to be set lower in frequency, thereby slowing the converters load transient response. most ltc3118 application circuits deliver the best performance with an inductor value between 3.3 h and 10 h. in gen - eral, a 3.3 h inductor is recommended for v out up to 5v, 6.8h for v out = 12 v and 10 h for v out = 18 v. inductor values for other output voltages can be scaled accordingly. regardless of inductor value, the saturation current rat - ing should be such that it is greater than the worst-case a verage inductor current plus half of the ripple cur - rent. the peak-to-peak inductor current ripple for each operational mode can be calculated from the following formula, where f is the switching frequency (1.2 mhz), l is the inductance in h, and t low is the switch pin minimum low time in s. the switch pin minimum low time is typically 0.1s. i l(p-p)buck = v out l v in ? v out v in ? ? ? ? ? ? 1 f ? t low ? ? ? ? ? ? amps i l(p-p)boost = v in l v out ? v in v out ? ? ? ? ? ? 1 f ? t low ? ? ? ? ? ? amps it should be noted that the worst-case inductor peak-to- peak inductor ripple current occurs when the duty cycle in buck mode is maximum ( highest v in ), and in boost mode when the duty cycle is 50% (v out = 2 ? v in ). as an example, if v in (minimum) = 2.7 v and v in (maximum) = 18v, v out = 5 v and l = 3.3 h, the peak-to-peak inductor ripples at the voltage extremes (18 v v in for buck and 2.7v v in for boost) are: buck = 600ma peak-to-peak boost = 200ma peak-to-peak one-half of this inductor ripple current must be added to the highest expected average inductor current in order to select the proper saturation current rating for the inductor (about 4a). in addition to its influence on power conversion efficiency, the inductor dc resistance can also impact the maximum output current capability of the buck-boost converter par - ticularly at low input voltages. in buck mode, the output current of the buck-boost converter is primarily limited by the inductor current reaching the average current limit threshold defined by vc. however, in boost mode, espe - cially at large step-up ratios, the output current capability can also be limited by the total resistive losses in the power stage. these losses include switch resistances, inductor dc resistance and pcb trace resistance. avoid inductors with a high dc resistance ( dcr), as they can degrade the maximum output current capability from what is shown in the typical performance characteristics section. as a guideline, the inductor dcr should be significantly less than the typical power switch resistance of 100 m. the only exceptions are applications that have a maximum output current much less than what the ltc3118 is ca - pable of delivering. different inductor core materials and styles have an impact on the size and price of an inductor at any given current rating. shielded construction is generally preferred as it minimizes the chances of interference with other circuitry. the choice of inductor style depends upon the price, sizing and emi requirements of a particular application. table 1 provides a small sampling of inductors that are well suited to many ltc3118 applications. output capacitor selection a low effective series resistance ( esr) output capacitor should be connected at the output of the buck-boost con - verter in order to minimize output voltage ripple. multilayer ceramic capacitors are an excellent option as they have low esr and are available in small footprints. the capacitor a pplica t ions i n f or m a t ion ltc 3118 3118f
26 for more information www.linear.com/ltc3118 table 1. representative buck-boost surface mount inductors part number value (h) dcr (m) max dc current (a) size (w l h) mm manufacturer mss7341t xal7030 3.3 6.8 18 42 3.7 4.4 7 7 4 8 8 3 coilcraft www.coilcraft.com sd8328 3.3 4.7 14 19 4.0 3.6 8 8 3 8 8 3 coiltronics www.coiltronics.com lqh88pn lqh88pn lqh88pn 3.3 4.7 6.8 16 22 28 5 4.2 3.8 8 8 4 8 8 4 8 8 4 murata www.murata.com cdrh8d28np 3.3 4.7 18 25 4 3.4 8 8 3 8 8 3 sumida www.sumida.com vlp 840 3.3 6.8 15 24 5.2 3.6 8 8 4 8 8 4 tdk electronics www.tdk.co.jp fdsd0603 3.3 6.8 23 51 5.6 3.7 7 7 3 7 7 3 toko www.toko.co.jp 7447789003 7447789004 7447779006 3.3 4.7 6.8 30 35 35 4.2 3.9 3.3 7 7 3 7 7 3 7 7 4.5 w rth elektronik www.we-online.com a pplica t ions i n f or m a t ion value should be chosen large enough to reduce the output voltage ripple to acceptable levels. neglecting the capaci- tors esr and esl, the peak-to-peak output voltage ripple can be calculated by the following formula, where f is the frequency in mhz (1.2 mhz), c out is the capacitance in f, t low is the switch pin minimum low time in s (0.1s) and i load is the output current in amps. v p-p(buck) = i load t low c out volts v p-p(boost) = i load fc out v out ? v in + t low fv in v out ? ? ? ? ? ? volts examining the previous equations reveals that the output voltage ripple increases with load current and is gener- ally higher in boost mode than in buck mode. note that these equations only take into account the voltage ripple that occurs from the inductor current to the output being discontinuous. they provide a good approximation to the ripple at any significant load current but underestimate the output voltage ripple at very light loads where the output voltage ripple is dominated by the inductor current ripple. in addition to the output voltage ripple generated across the output capacitance, there is also output voltage ripple produced across the internal resistance of the output capacitor. the esr-generated output voltage ripple is pro - portional to the series resistance of the output capacitor, and is given by the following expressions where r esr is the series resistance of the output capacitor and all other terms as previously defined. v p-p(buck) = i load r esr 1 ? t low f ? i load r esr volts v p-p(boost) = i load r esr v out v in 1 ? t low f ( ) ? i load r esr v out v in ? ? ? ? ? ? volts in most ltc3118 applications, an output capacitor between 47f and 100f will work well. input capacitor selection the v in1 or v in2 pin carries the full inductor current and provides power to internal control circuits in the ic. to minimize input voltage ripple and ensure proper operation of the ic, a low esr bypass capacitor with a value of at least 10 f should be located as close to the pin as possible. ltc 3118 3118f
27 for more information www.linear.com/ltc3118 the traces connecting this capacitor to v in1 or v in2 and the ground plane should be made as short as possible. when powered through long leads or from a high esr power source, a larger value bulk input capacitor may be required. in such applications, a 47 f to 100 f electrolytic capacitor in parallel with a 1 f ceramic capacitor gener - ally yields a high performance, low cost solution. in ideal diode mode, the voltage ripple on each input must be kept below the v in comparators 800 mv hysteresis to prevent repetitive switching between v in1 and v in2 operation when the input voltages aare similar. recommended input and output capacitors the capacitors used to filter the input and output of the ltc3118 must have low esr and must be rated to handle the large ac currents generated by the switching convert - ers. this is important to maintain proper functioning of the ic and to reduce output voltage ripple. there are many capacitor types that are well suited to these applications including multilayer ceramic, low esr tantalum, os-con and poscap technologies. in addition, there are certain types of electrolytic capacitors, such as solid aluminum organic polymer capacitors, that are designed for low esr and high ac currents and these are also well suited to some ltc3118 applications. table 2 provides a partial listing of appropriate capacitors to use. the choice of capacitor technology is primarily dictated by a trade-off between size, leakage current and cost. in backup power applications, the input or output capacitor might be a super or ultra capacitor with a capacitance value measuring in the farad range. the selection criteria in these applications are generally similar except that voltage ripple is generally not a concern. some capacitors exhibit a high dc leak - age current which may preclude their consideration for applications that require a very low quiescent current in burst mode operation. table 2. representative bypass and output capacitors part number value (f) volt age (v) capacitor t ype esr (m) size (w l h) mm manufacturer 12103d226 mat 2a 22 25 x5r ceramic 3.2 2.5 2.8 avx www. avx.com c2220x226k3ractu a700d226m016 ate 030 22 22 25 16 x7r ceramic, aluminum polymer 30m 5.7 5 2.4 7.3 4.3 2.8 kemet www.kemet.com grm32er71e226ke15l 22 25 x7r ceramic 3.2 2.5 2.5 murata www.murata.com p lv 1e121mdl1 82 25 aluminum polymer, 25m 8 8 3 nichicon www.nichicon.com ecj-4yb1e226m 22 25 x5r ceramic 3.2 2.5 2.5 panasonic www.panasonic.com 25tqc22mv 16tqc100m 25svpf47m 22 100 47 25 16 25 poscap , 50m poscap, 45m os-con, 30m 7.3 4.3 1.9 7.3 4.3 3.1 6.6 6.6 5.9 sanyo www.sanyo.com tmk 325bj226mm-t 22 25 x5r ceramic 3.2 2.5 2.5 taiyo yuden www.t-yuden.com ckg 57nx5r1e476m 47 25 x5r ceramic 6.5 5.5 5.5 tdk www.tdk.com a pplica t ions i n f or m a t ion ltc 3118 3118f
28 for more information www.linear.com/ltc3118 ceramic capacitors are often utilized in switching con- verter applications due to their small size, low esr and low leakage currents. however, many ceramic capacitors intended for power applications experience a significant loss in capacitance from their rated value as the dc bias voltage on the capacitor increases. it is not uncommon for a small surface mount capacitor to lose more than 50% of its rated capacitance when operated near its maximum rated voltage. this effect is generally reduced as the case size is increased for the same nominal value capacitor. as a result, it is often necessary to use a larger value capacitance or a higher voltage rated capacitor than would ordinarily be required to actually realize the intended capacitance at the operating voltage of the application. x5r and x7r dielectric types are recommended as they exhibit the best performance over the wide operating range and temperature of the ltc3118. to verify that the intended capacitance is achieved in the application circuit, be sure to consult the capacitor vendors curve of capacitance versus dc bias voltage. compensation of the buck-boost converter the ltc3118 utilizes an average current architecture to regulate the output voltage. average current mode control has two loops that require frequency compensation, the inner average current loop and the outer voltage loop. the compensation for the inner average current loop is fixed within the ltc3118 to simplify the loop design and provide the highest possible bandwidth over a wide operating range . the outer voltage loop does require external compensation components, allowing the overall loop characteristics to be customized for the application. the average current mode control used in the ltc3118 can be conceptualized as a voltage-controlled current source (v ccs ), driving the output load formed primarily by r load and c out , as shown in figure 8. the voltage error amplifier output ( vc), provides a com- mand input to the v ccs . the full-scale range of vc is 0.6v (200mv to 800 mv). with a full-scale command on vc, figure 8. simplified representation of average current mode control loop a pplica t ions i n f or m a t ion 3118 f08 1v 800mv g m = 3.6a/0.6v + ? fb voltage error amp voltage controlled current source vc gnd r z r1 400k r2 100k r coesr 0.01 r load 5 c p1 c out 47f v out = 5v c p2 ? + g m ltc 3118 3118f
29 for more information www.linear.com/ltc3118 the ltc3118 buck-boost converter will generate an aver- age 3.6 a of inductor current ( typical) from the converter making the transconductance gain 6 a /v. as with peak current mode control, the inner average current control loop effectively turns the inductor into a current source over the frequency range of interest, resulting in a frequency response from the power stage that exhibits a single pole (C20db / decade) roll-off. the output capacitor (c out ) and load resistance ( r load ) form a dominant low frequency pole, where the effective series resistance of the output capacitor and its capacitance form a zero, usually at a high enough frequency to be ignored. a potentially troublesome right half plane zero (rhpz) is also encountered if the converter is operated in boost mode. the rhpz causes an increase in gain, like a zero, but a decrease in phase, like a pole. this can ultimately limit the maximum converter bandwidth that can be achieved with the ltc3118. the rhpz is not present when operat - ing in buck mode. the overall open loop gain at dc is the product of the following terms: voltage error amp gain: g m ? r ea = 80s ? 5m = 400v v (fixed) voltage divider gain: v fb v out = 1v v out current loop transconductance: g c = 6a v (fixed ) load resistance: r load = v out i load the frequency dependent terms that affect the loop gain include: output load pole (p1): 1 2 ? r load ? c out (application dependent) right half plane zero (rhpz): v in 2 ? r l v out 2 ? 2 ? l (application dependent) voltage error amplifier compensation : 2 poles and 1 zero (application dependent) the voltage amplifiers frequency response is designed to optimize the response for the overall loop. measure - ment of the power stage gain over line, load, component variation and frequency is strongly recommended prior to loop design. the design parameters for compensation design will focus on the series resistor and capacitors connected from vc to ground (r z , c p1 and c p2 ). being a buck- boost converter, the target loop crossover frequency for the compensation design will be dictated by the high - est boost ratio and load current that is expected, as this will result in the lowest rhpz frequency. the general goal is to set the crossover frequency and provide sufficient phase boost using the external compensation network. a pplica t ions i n f or m a t ion ltc 3118 3118f
30 for more information www.linear.com/ltc3118 compensation example this section will demonstrate how to derive and select the compensation components for a typical ltc3118 ap - plication. designing compensation for other applications is a matter of substituting different values in the equations provided based on the power stage bode plots. since the compensation design procedure uses a simplified model of the ltc3118, the results from the following compensa - tion design should always be verified with time domain step load response tests to validate the effectiveness of the compensation design. it is assumed that the value and type of output capacitor will be selected based on the guidelines provided elsewhere in this data sheet. particular attention needs to be paid to the voltage bias effect on ceramic capacitors typically used for output bypassing. similarly, it is assumed that the inductor value and current rating has been selected as well, based on the application requirements. example application details: v in = 3v to 15v v out = 5v maximum i out (boost mode) = 1a, r load = 5 maximum i out (buck mode) = 1a, r load = 5 (could supply 2a if v in > 5v) c out = 100 f but use 66 f in calculations to account for dc voltage bias effects. l = 3.3h since this application includes boost mode operation, the first step is to calculate the worst-case rhpz frequency as this will dictate the maximum loop bandwidth for the converter. rhpz(f) = v in 2 ? r load v out 2 ? 2 ? l = 3v 2 ? 5 5v 2 ? 2 ? 3.3h = 87khz in order to account for internal ic component variations, it is a good practice to set the converter bandwidth, or crossover frequency, at least 4 to 5 times lower than the rhpz frequency, to avoid excessive phase loss from the rhpz when operating in boost mode. in some instances such as higher output voltage applications, an even greater separation between the loop crossover frequency and the rhpz frequency may be necessary. in this example design, well plan to achieve a loop bandwidth (f cc ) of 20khz, well below the rhpz frequency. the 5 v , 1 a de- sign example bode plots are shown in figure 9. the top curve set shows the power stage gain ( and phase) in buck (> 5v in ) and 3v in boost mode operation. the dc gain in buck mode is simply the current loop transconductance (6a/v) multiplied by the load resistance (5). the v out resistor divider will be accounted for in voltage amplifier network. buck dc gain: 20log 6a/v ? 5? ( ) = 29db in boost mode the gain is reduced by v in / v out . boost dc gain at 3v in : 20log 6a/v ? 3v ? 5 5v ? ? ? ? ? ? = 25db the output load pole will move depending on the output load resistance. the power stage poles at full load are shown in the top set of curves in figure 9. output load pole: 1 2 ? r load ? c out = 1 2 ? 5 ? 66f = 480hz a pplica t ions i n f or m a t ion ltc 3118 3118f
31 for more information www.linear.com/ltc3118 these values were verified in the top set of curves in figure 9. the resulting power stage crossover frequency is around 40 khz in buck mode (v in > 5v), 20 khz in boost mode at 3.5v in . the uncompensated power stage crossover frequency is higher than the goal of 20 khz. more importantly, the uncompensated power stage dc gain is low, especially in boost mode. a pole-zero-pole network will now be added to the voltage amplifier to increase the dc gain, reduce the crossover frequency and reduce the overall gain at high frequencies: v a pole 1 = 1 2 r ea c p1 figure 9. bode plot showing power stage gain ( top ), v a loop (center), and total loop gain vs frequency a pplica t ions i n f or m a t ion 3118 f08 frequency voltage loop gain (db) 10hz 10khz 100khz 1mhz 100hz 1khz frequency ?40 total loop gain (db) ?20 10 0 10hz 10khz 100khz 1mhz ?70 ?60 100hz 1khz 30 20 ?30 ?10 60 50 70 40 ?50 frequency ?30 power stage gain (db) phase (deg) ?18 ?6 10hz 10khz 100khz 1mhz 100hz 1khz 6 0 ?24 ?12 24 18 30 12 ?36 ?180 ?60 0 ?120 60 120 phase (deg) ?120 ?100 ?60 ?40 ?80 ?20 0 phase margin (deg) ?180 ?60 ?120 180 120 210 0 60 ?30 ?18 ?6 6 0 ?24 ?12 24 18 36 30 12 ?36 ?vc/ v outa v out / v outa v out / vc boost mode buck mode buck mode gain phase gain phase gain phase margin boost mode ltc 3118 3118f
32 for more information www.linear.com/ltc3118 this pole is close to dc, r ea = voltage error amp output resistance, which is approximately 5 m. this pole is mentioned for completeness, but has no effect on the overall loop design: v a zero 1 = 1 2 r z c p1 this zero is placed below the crossover frequency to flatten the v a gain at the crossover to improve phase margin: v a pole 2 = 1 2 r z c p2 this pole is placed above the crossover frequency to reduce the gain to suppress noise and mitigate any rhpz effects. referring to the power stage gain curves in figure 9, the loop gain needs to be reduced by 4 db to achieve a total loop crossover frequency of 20 khz. assuming zero 1 is placed well below the crossover frequency and pole 2 is placed well above the crossover frequency, the voltage amplifiers gain at crossover is given by: v a gain at crossover: 20log v fb ? g m ? r z v out ? ? ? ? ? ? = 20log 1v ? 80a/v ? 40k 5v ? ? ? ? ? ? = ? 4db where g m is the v a transconductance, v fb / v out is the feedback divider gain, and r z is the external zero resistor. as shown, a 40 k value for r z will provide C4 db of gain at crossover. with r z selected, c p1 s value is determined by setting the zero 1 frequency at one-tenth the crossover frequency, or 2khz. c p1 = 1 2 ? r z ? f zero1 = 1 2 ? 40k ? 2khz ? 1.8nf finally, the high frequency pole 2 is set at 10 times the crossover frequency to provide a high frequency pole at 200khz. c p2 = 1 2 ? r z ? f pole2 = 1 2 ? 40k ? 200khz ? 22pf the second set of curves in figure 9 show the resulting v a response to the selected values. notice that the separation between zero 1 and pole 2 provides 60 degrees phase bump near the crossover frequency. combining the power stage and v a frequency responses, the measured overall loop gains are shown in the bottom set of curves of figure 9. as shown, the crossover frequency was reduced to 20 khz in buck mode, 10 khz in boost. the phase margin at crossover is around 70 degrees. the v a design provided the additional benefits of high gain (>50db) at dc and gain attenuation above the crossover frequency to prevent rhpz issues. a pplica t ions i n f or m a t ion ltc 3118 3118f
33 for more information www.linear.com/ltc3118 typical a pplica t ions system power (priority) or 3-cell li-ion to 5v v out regulator with automatic burst mode operation efficiency vs load current: v in1 = 5v, v in2 = 10.8v, v out = 5v 100ma to 1a load step, v in1 = 5v, v out = 5v, auto burst mode 3.3h 0.1f 0.1f 232k + 100k 402k 5v up to 1.5a, v in > 4.5v 100k 40.2k 47nf 47nf 4v to 5.5v 10nf 22f 100f pgnd power good indicators 22f 523k 10nf 22pf system power 7.5v to 12.6v li-ion + + + 4.7f bat-54 schottky diode bst1 bst2 v in1 sw1 sw2 3118 ta02a cm1 pgnd cm2 run1 cp1 cp2 v out vc gnd v1gd fb v2gd pgd cn2 cn1 v cc sel mode v in2 pgnd run2 ltc3118 100k 1.8nf load current (a) 0.0001 efficiency (%) 40 60 10 3118 ta02b 20 0 0.001 0.01 0.1 1 100 30 50 10 70 80 90 v in1 v in2 pwm burst 100s/div 3118 ta02c 5v out transient 200mv/div inductor current 1a/div load current 1a/div vc 200mv/div ltc 3118 3118f
34 for more information www.linear.com/ltc3118 typical a pplica t ions 12v wall adapter (when present) or 2-cell li-ion to 12v v out regulator with automatic burst mode operation efficiency vs load current: v in1 = 7v, v in2 = 12v, v out = 12v 12v in2 to 6v in1 sel pin switchover with v out = 12v and 800ma load 402k 100k 1100k 12v at 800ma 100k 60.4k 47nf 47nf 6v to 8.2v 10nf 22f 100f pgnd power good indicators 100f 750k 10nf 22pf 10v to 14v li-ion + + 4.7f bst1 bst2 v in1 sw1 sw2 3118 ta03a cm1 pgnd cm2 run1 cp1 cp2 v out vc gnd v1gd fb v2gd pgd cn2 cn1 v cc sel mode v in2 pgnd run2 ltc3118 100k 1.2nf + 12v wall adapter 6.8h 0.1f 0.1f load current (a) 0.0001 efficiency (%) 40 60 10 3118 ta03b 20 0 0.001 0.01 0.1 1 100 30 50 10 70 80 90 v in1 v in2 pwm burst 500s/div 3118 ta03c 12v out transient 500mv/div inductor current 1a/div sw1 10v/div sel 1a 2a 12v in2 inductive cable insertion with v out = 12v and 800ma load 100s/div 3118 ta03d 12v out transient 500mv/div inductor current 2a/div v in2 5v/div v in1 5v/div cable insertion v out = 12v switchover to v in2 v in2 = 12v v in1 = 6v ltc 3118 3118f
35 for more information www.linear.com/ltc3118 efficiency vs load current: v in1 = 5v, v in2 = 12v, v out = 3.3v 100ma to 1a load step, v in = 12v, v out = 3.3v, auto burst mode typical a pplica t ions dual battery system to 3.3v v out , runs from lead acid (priority) when present automatic burst mode operation 232k 3.3v up to 2.5a, v in > 4.5v 100k 18.2k 47nf 47nf 3v to 16.5v 10nf 22f 100f pgnd power good indicators 22f 301k 10nf 47pf 10.5v to 14.5v stack of 3-10 nimh or alkaline batteries 4.7f bst1 bst2 v in1 sw1 sw2 3118 ta04a cm1 pgnd cm2 run1 cp1 cp2 v out vc gnd v1gd fb v2gd pgd cn2 cn1 v cc sel mode v in2 pgnd run2 ltc3118 768k 100k 200k 3.9nf + lead acid battery ? 3.3h 0.1f 0.1f load current (a) 0.0001 efficiency (%) 40 60 10 3118 ta04b 20 0 0.001 0.01 0.1 1 100 30 50 10 70 80 90 pwm burst v in1 v in2 100s/div 3118 ta04c 3.3v out transient 200mv/div inductor current 1a/div load current 1a/div vc 200mv/div ltc 3118 3118f
36 for more information www.linear.com/ltc3118 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 23 24 1 2 bottom view?exposed pad 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or c = 0.35 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd24) qfn 0506 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.65 0.05 2.00 ref 3.00 ref 4.10 0.05 5.50 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 2.00 ref 3.00 ref 3.65 0.10 3.65 0.05 ufd package 24-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1696 rev a) ltc 3118 3118f
37 for more information www.linear.com/ltc3118 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. fe28 (eb) tssop rev k 0913 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 192022 21 151618 17 9.60 ? 9.80* (.378 ? .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev k) exposed pad variation eb ltc 3118 3118f
38 for more information www.linear.com/ltc3118 ? linear technology corporation 2015 lt 0215 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3118 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3111 1.5a (i out ), 15v synchronous buck-boost dc/dc converter v in = 2.5v to 15v, v out = 2.5v to 15v, i q = 49a, i sd < 1a, dfn and msop packages ltc 3112 2.5a (i out ), 15v synchronous buck-boost dc/dc converter v in = 2.7v to 15v, v out = 2.5v to 14v, i q = 40a, i sd < 1a, dfn and tssop packages ltc 3113 3a (i out ), 5v synchronous buck-boost dc/dc converter v in = 1.8v to 5.5v, v out = 1.8v to 5.25v, i q = 30a, i sd < 1a, dfn and tssop packages ltc 3114-1 1a (i out ), 40v synchronous buck-boost dc/dc converter v in = 2.2v to 40v, v out = 2.7v to 15v, i q = 30a, i sd < 3a, dfn and tssop packages ltc 3115-1 2a (i out ), 40v synchronous buck-boost dc/dc converter v in = 2.7v to 40v, v out = 2.7v to 40v, i q = 30a, i sd < 3a, dfn and tssop packages ltc 3122 2.5a i sw , 3mhz, synchronous step-up dc/dc converter with output disconnect, burst mode operation, up to 95% efficiency operating range v in = 1.8v to 5.5v (500mv after start-up), v out = up to 15v, i q = 25a, i sd <1a, 3mm 4mm dfn and msop packages ltc3124 5a i sw , 3mhz, 2-phase synchronous step-up dc/dc converter, output disconnect, burst mode operation, up to 95% efficiency operating range v in = 1.8v to 5.5v (500mv after start-up), v out up to 15v, i q = 25a, i sd < 1a, 3mm 5mm dfn and tssop packages ltc3129 200ma (i out ), 15v synchronous buck-boost dc/dc converter v in = 2.42v to 15v, v out = 2.5v to 14v, i q = 1.3a, i sd = 10na, qfn and msop packages ltc 4412 28v low loss powerpath controller in thinsot? operating range 3v to 36v, i q = 11a, 6-lead thinsot package ltc4417 prioritized powerpath controller v in = 2.5v to 36v, C42v reverse protection, i q = 28a, i sd < 1a, qfn and ssop packages 12v v in to 5v v out converter with capacitor backup runs from v in1 (priority) in normal mode, v in2 during backup event 10mf, 18v back-up capacitor supports 200ma load for >1 second 200ms/div 3118 ta05b v in2 10v/div v in1 10v/div v out 5v/div inductor current 1a/div 768k + 100k 402k 100k 40.2k 40.2k 47nf 47nf 10.5v to 14.5v 10nf 22f 47f 5v pgnd bat-54 schottky diode power good indicators v cc back fed from v out for low v in operation 22f 2m 10nf 10mf capacitor backup 22pf lead acid battery or 12v system power 18v max, runs down to 2.2v + 4.7f bst1 bst2 v in1 sw1 sw2 3118 ta05a cm1 pgnd cm2 run1 cp1 cp2 v out vc gnd v1gd fb v2gd pgd cn2 cn1 v cc sel mode v in2 pgnd run2 ltc3118 1.8nf 3.3h 0.1f 0.1f 40.2k can?t run from v in2 until v out starts up ltc 3118 3118f

▲Up To Search▲

Price & Availability of LTC3118-15

	To Download LTC3118-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .